With ever-increasing demands for higher operating speed and lightweight miniaturization of electronic devices, the semiconductor package structure including multiple chips (i.e. a multi-chip package structure) has become more and more popular. In a multi-chip package structure, a processor, a memory device and a logic chip can be assembled in one single package structure for minimizing the limitation of system operational speed caused by long connection paths existing on a printed circuit board. Further, the multi-chip package structure can shorten the length of the connection between chips, thereby lowering the signal delay and accessing time.
However, especially for high-frequency elements, radio frequency generated between chips may result in serious EMI, thus affecting the performance of the chips. Hence, a specific design has to be added for reducing the EMI problem. A conventional skill directly adds a conductive element between to two chips to interrupt the EMI between those two chips. However, the conventional skill has to first complete the related structures about two chips and then encapsulate those two chips together, and thus those two chips are exposed to the ambient for quite a long time, thus increasing the probability of damaging the chips. Further, the conventional skill actually increases the size of the package structure fabricated, thus having a difficulty in meeting the requirement of miniaturization.